Chip Industry Technical Paper Roundup: July 8
Schottky barriers at Si/metal interfaces; agentic HLS; probabilistic memory for edge; agentic HW design automation as repository-level code evolution; HW fingerprinting for photonic ICs; functional safety; open-source, customizable RISC-V SoC platform.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Effect of Exchange-Correlation Functionals on Schottky Barriers at Si/Metal Interfaces | NIST, University of Maryland, Johns Hopkins University |
| AgRefactor: Self-Evolving Agentic Workflow for HLS Compatibility and Performance | Carnegie Mellon University, UCLA |
| Probabilistic Memory for Trustworthy Edge Intelligence | University of Notre Dame, Georgia Tech, and Villanova University |
| Agentic Hardware Design as Repository-Level Code Evolution | Nvidia Research |
| Enhancing Co-packaging Optics Enabled Silicon Photonics Security Assurance Hardware Fingerprinting | University of Florida |
| SafeGen: LLM-Driven Assertion Generation and Fault Criticality Evaluation for Functional Safety | Arizona State University, Texas Instruments India |
| Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon | ETH Zurich, lowRISC, University of Bologna |
Find more semiconductor research papers here.
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