Pre-Silicon Power Side-Channel Leakage In Processors (University of LĂĽbeck)
Researchers from University of Lübeck published a technical paper titled “SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow.”
Abstract Excerpt: “This paper presents SPARC, an automated framework for pre-silicon PSCL evaluation and root-cause analysis. SPARC leverages macro-cell-level Information Flow Tracking (IFT) augmented with enhanced shadow logic that tags switching activity originating from secret-dependent data. By isolating this activity, SPARC applies statistical leakage tests to detect PSCL, while simultaneously attributing the leakage to specific hardware signals and mapping those signals to the corresponding software instructions. ”
Find the technical paper here. July 2026. arXiv:2607.23218v1
Nešković, Andrija, Christian Ewert, Mladen Berekovic, and Saleh Mulhem. “SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow.” In IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’26), November 8–12, 2026, San Jose, CA, USA. ACM, 2026. https://doi.org/10.1145/3831252.3834007.
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