Chip Industry Technical Paper Roundup: Aug. 4
Hybrid NAND flash-DRAM memory; neuromorphic many-core computing; modular HW-SW leakage verification; bridging p-type gap in oxide electronics w/2D semis; 3D structures from wafer-fabricated precursors; LLM benchmarking for Verilog design flows; pre-silicon power side-channel analysis.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| The SpiNNaker2 Chip: A Many-Core Platform for Flexible and Scalable Brain-Inspired Computing 🔗 | TU Dresden, University of Manchester |
| Granite: A Modular Methodology for Foundational Verification of Hardware-Software Leakage Contracts 🔗 | MIT, Google, University of Washington |
| NAD Memory: A Hybrid Memory Device Combined with NAND Flash Memory and DRAM 🔗 | University of Seoul |
| Bridging the p-Type Gap in Oxide Electronics with 2D Semiconductors 🔗 | Stanford University, Hanyang University |
| Deployable 3D Architectures from Wafer-Fabricated Precursors 🔗 | University of Houston, Toyota, Imperial College London |
| Benchmarking LLMs for Verilog Design Flows 🔗 | NMIMS Hyderabad, IIT Roorkee, BITS Pilani |
| SPARC: Automated Root-Cause Analysis of Pre-Silicon Power Side-Channel Leakage in the Processor Design Flow 🔗 | University of Lübeck |
Find more semiconductor research papers here.
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